TestBench For 4 Bit Right Shift Register In verilog Textfixture

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: VHDL Language
// Engineer: Manohar Mohanta
//
// Create Date:   13:24:21 04/10/2016
// Design Name:   shift_register
// Module Name:   G:/Verilog/shift_register_tb.v
// Project Name:  Verilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: shift_register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module shift_register_tb;

// Inputs
reg [3:0] a;
reg [1:0] shift;
reg clk;

// Outputs
wire [3:0] y;

// Instantiate the Unit Under Test (UUT)
shift_register uut (
.a(a),
.y(y),
.shift(shift),
.clk(clk)
);

initial begin
// Initialize Inputs
a = 3'b0110;shift = 2'b00;clk = 1;#100;
      a = 3'b0110;shift = 2'b01;#100;
a = 3'b0110;shift = 2'b10;#100;
a = 3'b0110;shift = 2'b11;#100;
// Add stimulus here

end
      always #50 clk=~clk;
endmodule

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